This invention relates to a structure and its method of a circuit for detecting the potential of a node on a circuit in a semiconductor integrated circuit device.
Conventionally, as the method for detecting the potential of an arbitrary node on a circuit of a semiconductor integrated circuit device, a test pad was mounted on a desired node on the layout, and it was directly contacted with the detection probe. Or, as a non-contact potential detecting method, the method of detecting by using a strobo SEM or an EB (electron beam) tester is known, but as the chip layout pattern becomes finer, the detecting sensitivity or resolution is lowered, or as the logic circuit is integrated and becomes complicated, the detection of the potential has become difficult. In this case, too, a test pad is required on a desired node position on the circuit.
For example, a conventional composition of signal detecting pad is shown in FIGS. 10(a)-10(b). Element 131 is a wiring pattern of a signal wire in the chip, and elements 132 and 133 are pads for detecting signals such as potentials. As shown in the drawings, the size of the pads installed for detecting the potential of a signal wire is often larger than the signal wiring pattern as the pattern becomes finer so as to easily realize mechanical probing by a direct contact, or non-contact probing by an EB tester.
FIG. 10(a) shows an example in which the layer of the detecting pad and the layer of the signal wiring are identical, and FIG. 10(b) shows an example in which the layer of the detecting pad and the layer of the signal wiring are different, and the two layers are connected by a contact.
Hitherto, however, this test pad was not defined as a logic cell. Accordingly, in the circuit block composed by automatic disposition and wiring of cells by a computer conforming to a net list on the basis of a circuit diagram, test pads could not be present. Therefore, by making up a desired circuit block and modifying the layout, test pads were additionally inserted into desired positions. It hence caused a significant layout change, and induced logic errors and layout errors in the process, which was a great disturbance for the development of chips.
The pad installed for detecting potentials is useful when its area is larger if used in a mechanical probing of a direct contact. However, when using an EB tester which is a non-contact probing, by only merely increasing the size of the signal detecting pad, the desired potentials and signals cannot be sufficiently detected, and the following problems were noted. First, by the charge-up phenomenon on the chip surface by EB irradiation, the signal waveform is distorted. Secondly, the relative potential of the detected signal waveform can be accurately measured, but it is difficult to obtain the absolute value of the potential of the signal waveform.
The pad to be installed for detection of signals such as potentials can be used whether in mechanical probing of direct contact, or in non-contact probing such as an EB tester. However, since the node position of the signal to be detected in particular is at an arbitrary position on the layout, it is extremely difficult to search the node position and probe. The job efficiency was very poor because of moving and searching of position for probing, and complicated operation of the equipment for such moving. Or, if the signal waveform to be detected could be obtained, it was extremely difficult to know how much the signal waveform was delayed with respect to the clock signal as the reference for the waveform of the chip, and what the phase relationship therebetween was.
When, moreover, the signal detecting test pad is laid out within the circuit block, if there are a plurality of test pads and the layout states around the test pads are similar, it is difficult to judge visually which test pad is connected to which specific node.